1. Field of the Invention
The present invention generally relates to nonvolatile ferroelectric memory devices, and more specifically, to a nonvolatile ferroelectric memory device configured to reduce the frequency of whole chip operation by performing a cell operation at transition points of a reset signal and a write enable signal instead of performing the cell operation at a transition point of a chip enable signal. As a result, data latched in a sense amplifier can be outputted without performing the whole chip operation, thereby improving reliability of the cell and reducing power consumption.
2. Description of the Prior Art
Generally, a ferroelectric randaom access memory (hereinafter, referred to as xe2x80x98FRAMxe2x80x99) has attracted considerable attention as a next generation memory device because it has a data processing speed as fast as a DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is removed low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
As shown in FIG. 1, a polarization induced by an electric field does not vanish but keeps some strength (xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization.
These xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states may be assigned to binary values of xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device.
As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC1 having the first terminal of the two terminals connected to the drain terminal of the transistor T1 and the second terminal of the two terminals connected to the plateline PL.
The data input/output operation of the conventional FRAM is as follows.
FIG. 3a is a timing diagram illustrating a write mode of the conventional FRAM.
Referring to FIG. 3a, when a chip enable signal CEB applied externally is enabled from a high to low level, an inputted address is decoded and its corresponding wordline WL is enabled. In other words, a potential of the wordline WL transits from a low to high level, thereby selecting the cell.
In this way, while the wordline is held at a high level, a high level signal of a predetermined interval and a low level signal of a predetermined interval are sequentially applied to its corresponding plate line PL.
In order to write a binary logic value xe2x80x9c1xe2x80x9d in the selected cell, data signals DIN of high level and low level are inputted to its corresponding bitline BL.
In other words, in an interval where high level signals are applied to a bitline BL, if a low level signal is applied to a plateline PL, a logic value of xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor FC1.
If a low level signal is applied to a bitline BL and a high level signal is applied to a plateline PL, a logic value of xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor FC1.
FIG. 3b is a timing diagram illustrating a read mode of the conventional FRAM.
Referring to FIG. 3b, when a chip enable signal CEB externally transits from a xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d level, all bitlines are equalized to a xe2x80x9clowxe2x80x9d level by an equalization signal before selection of a required wordline.
After each bitline BL is activated, an address is decoded and the required wordline WL is enabled by the decoded address, that is, the required wordline WL transits from a xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d level, thereby selecting a corresponding unit cell.
A high level signal is applied to a plateline of the selected cell to destroy a data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the FRAM.
If the logic value xe2x80x9c0xe2x80x9d is stored in the FRAM, a corresponding data will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics.
As shown in the hysteresis loop of FIG. 1, the state moves from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 when the data is destroyed while the state moves from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 when the data is not destroyed.
After the lapse of a predetermined time, if a sense amplifier enable signal SEN is activated and a sense amplifier is enabled, the destroyed data amplified by the enabled sense amplifier outputs a logic value xe2x80x9c0xe2x80x9d.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, when a xe2x80x98highxe2x80x99 signal is applied to the required wordline WL, the plateline PL is disabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d.
FIG. 4 is a block diagram illustrating a chip control signal generating circuit for generating a chip control signal in a conventional nonvolatile ferroelectric memory device.
A chip enable signal buffer 1 receives a signal CEBPAD inputted in a chip enable pad and then outputs a chip enable signal CEB.
An address buffer 2 receives an address ADDPAD less than m:0 greater than  inputted in an address pad and then outputs an address ADD less than m:0 greater than .
A chip enable signal transition detector 3 receives the chip enable signal CEB, detects a transition point of the chip enable signal CEB, and then outputs a chip enable signal transition detecting signal CTD.
An address transition detector 4 receives the address ADD less than m:0 greater than , detects a transition point of the address ADD less than m:0 greater than , and then outputs an address transition detecting signal ATD.
A synthesizer 5 synthesizes the chip enable signal transition detecting signal CTD and the address transition detecting signal ATD, and then outputs a synthesized transition detecting signal TDS.
A chip control signal generator 6 outputs chip control signals by using the transition detecting signal TDS synthesized in response to the chip enable signal CEB.
Here, the address ADD less than m:0 greater than  outputted from the address buffer 2 is decoded by a decoder to select a wordline or a bitline.
As described above, according to the conventional ferroelectric memory device, the whole chip operates whenever the chip enable signal CEB transits from a high to low level. Here, when data stored in the ferroelectric capacitor is read, the capacitor operates as a destructive mode, thereby causing the fatigue phenomenon of ferroelectric material. After the data stored in the capacitor is read, the original data should be re-written. As a result, the control becomes complicated, the access time becomes delayed and current consumption increases.
Accordingly, it is an object of the present invention to provide a nonvolatile ferroelectric memory device configured to reduce the frequency of whole chip operation by performing a cell operation at transition points of a reset signal and a write enable signal instead of performing the cell operation at a transition point of a chip enable signal, thereby improving reliability of the cell and reducing power consumption.
The disclosed nonvolatile ferroelectric memory device comprising a cell array including a plurality of ferroelectric memory cells for storing data through a bitline and reading the stored data, selected by a wordline and a plateline includes: an address latch for receiving an inputted address through an address pad to select the wordline and the bitline before the cell operation, and for latching the address during the cell operation; a reset signal transition detecting means for detecting a start point where a reset operation and a cell operation are both performed, and for outputting a reset signal transition detecting signal; a write enable signal transition detecting means for detecting a point where a write operation starts and for outputting a write enable signal transition detecting signal; a synthesizing means for synthesizing an address transition detecting signal detecting a transition point of an address selectively latched by the address latch, the reset signal transition detecting signal and the write enable signal transition detecting signal, and for outputting a transition synthesizing signal; and a chip control signal generating means for generating chip control signals in response to the transition synthesizing signal.